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DSP56858/d rev. 1.0, 1/2002 ? motorola, inc., 2002. all rights reserved. DSP56858 preliminary technical data DSP56858 16-bit digital signal processor ? 120 mips at 120mhz 40k x 16-bit program sram 24k x 16-bit data sram 1k x 16-bit boot rom access up to 2m words of program memory or 8m data memory chip select logic for glue-less interface to rom and sram six (6) independent channels of dma two (2) enhanced synchronous serial interfaces (essi) two (2) serial communication interfaces (sci) serial port interface (spi) 8-bit parallel host interface general purpose 16-bit quad timer jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging computer operating properly (cop)/watchdog timer time-of -day (tod) 144 lqfp and 144 mapbga packages up to 47 gpio figure 1. DSP56858 block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit dsp56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit 4 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] mode a-c or d0-d15 [15:0] 6 program memory 40,960 x 16 sram boot rom 1024 x 16 rom data memory 24,576 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 gpioh0-h2 8 14 v ddio 12 decoding peripherals ipab ipwdb iprdb 4 system bus control memory pab pab cdbw cdbr cdbw v ss 8 gpioa0-a3 6 essi0 or gpioc 6 essi1 or gpiod host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll 2 ipbus clk cop/tod clk core clk dma requests
2 DSP56858 preliminary technical data motorola part 1 overview 1.1 DSP56858 features 1.1.1 digital signal processing core efficient 16-bit dsp engine with dual harvard architecture 120 million instructions per second (mips) at 120mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter parallel instruction set with unique dsp addressing modes hardware do and rep loops three (3) internal address buses and one (1) external address bus four (4) internal data buses and one (1) external data bus instruction set supports both dsp and controller functions four (4) hardware interrupt levels five (5) software interrupt levels controller-style addressing modes and instructions for compact code efficient c-compiler and local variable support software subroutine and interrupt stack with depth limited only by memory jtag/enhanced once debug programming interface 1.1.2 memory harvard architecture permits up to three (3) simultaneous accesses to program and data memory on-chip memory ? 40k 16-bit program ram ? 24k 16-bit data ram ? 1k 16-bit boot rom off-chip memory expansion (emi) ? access up to 2m words of program or 8m data memory (using chip selects) ? chip select logic for glue-less interface to rom and sram 1.1.3 DSP56858 peripheral circuit features general purpose 16-bit quad timer* two serial communication interfaces (sci)* serial peripheral interface (spi) port* two (2) enhanced synchronous serial interface (essi) modules* computer operating properly (cop)/watchdog timer
DSP56858 description motorola DSP56858 preliminary technical data 3 jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging six (6) independent channels of dma 8-bit parallel host interface* time-of-day (tod) up to 47 gpio * each peripheral i/o can be used alternately as a gpio if not needed 1.1.4 energy information fabricated in high-density cmos with 3.3v, ttl-compatible digital inputs wait and stop modes available 1.2 DSP56858 description the DSP56858 is a member of the dsp56800e core-based family of digital signal processors (dsps). this device combines the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals on a single chip to create an extremely cost-effective solution. the low cost, flexibility, and compact program code make this device well-suited for many applications. the DSP56858 includes peripherals that are especially useful for teledatacom devices; internet appliances; portable devices; tad; voice recognition; hands-free devices; and general purpose applications. the dsp56800e core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers, enabling rapid development of optimized control applications. the DSP56858 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the DSP56858 also provides two external dedicated interrupt lines, and up to 47 general purpose input/output (gpio) lines, depending on peripheral configuration. the DSP56858 dsp controller includes 40k words of program ram, 24k words of data ram and 1k of boot ram. it also supports program execution from external memory. this dsp controller also provides a full set of standard programmable peripherals that include an 8-bit parallel host interface, two enhanced synchronous serial interfaces (essi), one serial peripheral interface (spi), two serial communications interfaces (sci), and one quad timer. the host interface, quad timer, ssi, spi, sci i/o and four chip selects can be used as general purpose input/outputs when its primary function is not required. 1.3 ?best in class? development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow a programmer to create his own unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast and efficient development.
4 DSP56858 preliminary technical data motorola 1.4 product documentation the four documents listed in table 1 are required for a complete description of and proper design with the DSP56858. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/ . table 1. DSP56858 chip documentation 1.5 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the dsp56800e architecture, 16-bit dsp core processor and the instruction set dsp56800erm/d DSP56858 user?s manual detailed description of memory, peripherals, and interfaces of the DSP56858 dsp5685xum/d DSP56858 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56858/d DSP56858 product brief summary description and block diagram of the DSP56858 core, memory, peripherals and interfaces. DSP56858pb/d overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
introduction motorola DSP56858 preliminary technical data 5 part 2 signal/connection descriptions 2.1 introduction the input and output signals of the DSP56858 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 each table row describes the package pin and the signal or signals present. 1. v dd = v dd core, v ss = v ss core, v ddio = v dd io, v ssio = v ss io, v dda = v dd ana, v ssa = v ss ana 2. moda, modb and modc can be used as gpio after the bootstrap process has completed. 3. the following host interface signals are multiplexed: hrwb to hrd , hds to hwr , hreq to htrq and hack to hrrq. table 2. DSP56858 functional group pin allocations functional group number of pins power (v dd, v ddio, or v dda ) (8, 12, 1) 1 ground (v ss, v ssio, or v ssa ) (8, 14, 2) 1 pll and clock 3 external bus signals 39 external chip select* 4 interrupt and program control 7 2 host interface (hi)* 16 3 enhanced synchronous serial interface (essi0) port* 6 enhanced synchronous serial interface (essi1) port* 6 serial communications interface (sci0) ports* 2 serial communications interface (sci1) ports* 2 serial peripheral interface (spi) port* 4 quad timer module port* 4 jtag/on-chip emulation (once) 6 *alternately, gpio pins
6 DSP56858 preliminary technical data motorola figure 2. DSP56858 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. pin direction/type is represented as the preferred functionality. gpio may provide bidirectional use of any pin. DSP56858 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select address bus analog power 1 pll/clock host interface sci 2 essi 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrwb (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto host interface rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) std1 (gpiod0) srd1 (gpiod1) sck1 (gpiod2) sc10 (gpiod3) sc11 (gpiod4) sc12 (gpiod5) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 1 1 16 21 2 1 14 12 8 8 xtal
introduction motorola DSP56858 preliminary technical data 7 part 3 signals and package information all digital inputs have a weak internal pull-up circuit associated with them. these pull-up circuits are enabled by default. exceptions: 1. when a pin has gpio functionality, the pull-up may be disabled under software control. 2. mode a, mode b and mode c pins have no pull-up. 3. tck has a weak pull-down circuit always active. 4. bidirectional i/o pullups automatically disable when the output is enabled. this table is presented consistently with the signals identified by functional group figure. 1. bold entries in the type column represents the state of the pin just out of reset. 2. ouput(z) means an output in a high-z condition. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description v dd e1 14 v dd logic power (v dd ) ? these pins provide power to the internal structures of the chip, and should all be attached to v dd . v dd m6 36 v dd f12 52 v dd a9 72 v dd m2 87 v dd j12 88 v dd e12 109 v dd a12 125 v ss g1 15 v ss logic power ? ground (v ss ) ? these pins provide grounding for the internal structures of the chip and should all be attached to v ss. v ss l6 16 v ss d12 53 v ss a7 54 v ss f1 71 v ss m7 89 v ss k12 126 v ss a8 127
8 DSP56858 preliminary technical data motorola v ddio b1 5 v ddio i/o power (v ddio ) ? these pins provide power for all i/o and esd structures of the chip and should all be attached to v ddio (3.3v) . v ddio h1 6 v ddio m3 20 v ddio m8 45 v ddio m11 61 v ddio h12 67 v ddio c12 68 v ddio a11 80 v ddio a5 105 v ddio a3 113 v ddio c1 129 v ddio m10 139 v ssio d1 7 v ssio i/o power ? ground (v ssio ) ? these pins provide grounding for all i/o and esd structures of the chip and should all be attached to v ss. v ssio j1 21 v ssio m5 46 v ssio m9 47 v ssio l12 62 v ssio g12 69 v ssio b12 70 v ssio a10 82 v ssio a4 106 v ssio a1 115 v ssio a2 128 v ssio m4 130 v ssio m12 140 v ssio a6 141 v dda k1 24 v dda analog power (v dda ) ? these pins supply an analog power source. v ssa m1 25 v ssa analog ground (v ssa ) ? this pin supplies an analog ground. v ssa l1 26 table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 9 a0 e5 10 output(z) address bus (a0-a20) ? these signals specify a word address for external program or data memory access. a1 e4 11 a2 e3 12 a3 e2 13 a4 j2 29 a5 h3 30 a6 g4 31 a7 h4 32 a8 g5 48 a9 l5 49 a10 j6 50 a11 k6 51 a12 j8 63 a13 k8 64 a14 l9 65 a15 k9 66 a16 k10 75 a17 k11 76 a18 j9 77 a19 j10 78 a20 j11 79 table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
10 DSP56858 preliminary technical data motorola d0 h7 81 input / output(z) data bus (d0-d15) ? these pins provide the bidirectional data for external program or data memory accesses. d1 g7 94 d2 f9 95 d3 f10 96 d4 f11 97 d5 e10 98 d6 d7 120 d7 b7 121 d8 e7 122 d9 f8 123 d10 f7 124 d11 d5 137 d12 b4 138 d13 c4 142 d14 f6 143 d15 b3 144 rd d3 8 output read enable (rd ) ? is asserted during external memory read cycles. this signal is pulled high during reset. wr d4 9 output write enable (wr ) ? is asserted during external memory write cycles. this signal is pulled high during reset. cs0 gpioa0 h8 83 output input /output external chip select (cs0 ) ? this pin is used as a dedicated gpio. port a gpio (0 ) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. cs1 gpioa1 h9 84 output input /output external chip select (cs1 ) ? this pin is used as a dedicated gpio. port a gpio (1) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. cs2 gpioa2 h11 85 output input /output external chip select (cs2 ) ? this pin is used as a dedicated gpio. port a gpio (2) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 11 cs3 gpioa3 h10 86 output input /output external chip select (cs3 ) ? this pin is used as a dedicated gpio. port a gpio (3) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd0 gpiob0 j3 33 input input/output host address (hd0) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (0) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd1 gpiob1 k2 34 input input/output host address (hd1) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (1) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd2 gpiob2 l2 35 input input/output host address (hd2) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (2) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd3 gpiob3 j4 40 input input/output host address (hd3) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (3) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd4 gpiob4 l4 41 input input/output host address (hd4) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (4) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd5 gpiob5 j5 42 input input/output host address (hd5) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (5) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
12 DSP56858 preliminary technical data motorola hd6 gpiob6 k5 43 input input/output host address (hd6) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (6) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hd7 gpiob7 h5 44 input input/output host address (hd7) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (7) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. ha0 gpiob8 g10 90 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (8) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. ha1 gpiob9 g11 91 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (9) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. ha2 gpiob10 g9 92 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (10) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. hrwb hrd gpiob11 g8 93 input input input/output host read/write (hrwb) ? when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this signal is the read/write input . these pins are disconnected internally during reset. host read data (hrd ) ? this signal is the read data input when the hi08 is programmed to interface to a double-data- strobe host bus and the hi function is selected. port b gpio (11) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 13 hds hwr gpiob12 c8 116 input input input/output host data strobe (hds ) ? when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this input enables a data transfer on the hi when hcs is asserted. these pins are disconnected internally during reset. host write enable (hwr ) ? this signal is the write data input when the hi08 is programmed to interface to a double- data-strobe host bus and the hi function is selected. port b gpio (12) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hcs gpiob13 d8 117 input input/output host chip select (hcs ) ? this input is the chip select input for the host interface. these pins are disconnected internally during reset. port b gpio (13) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. hreq htrq gpiob14 b8 118 open drain output open drain output input/output host request (hreq ) ? when the hi08 is programmed for hrms=0 functionality (typically used on a single-data-strobe bus), this open drain output is used by the hi to request service from the host processor. the hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. these pins are disconnected internally during reset. transmit host request (htrq ) ? this signal is the transmit host request output when the hi08 is programmed for hrms=1 functionality and is typically used on a double-data- strobe bus. port b gpio (14) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
14 DSP56858 preliminary technical data motorola hack hrrq gpiob15 c7 119 input open drain output input/output host acknowledge (hack ) ? when the hi08 is programmed for hrms=0 functionality (typically used on a single-data- strobe bus), this input has two functions: (1) provide a host acknowledge signal for dma transfers or (2) to control handshaking and provide a host interrupt acknowledge compatible with the mc68000 family processors. these pins are disconnected internally during reset. receive host request (hrrq) ? this signal is the receive host request output when the hi08 is programmed for hrms=1 functionality and is typically used on a double-data- strobe bus. port b gpio (15) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. tio0 gpiog0 b9 114 input /output input/output timer input/outputs (tio0) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpiog0 ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. tio1 gpiog1 c9 112 input /output input/output timer input/outputs (tio1) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (1) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. tio2 gpiog2 d9 111 input /output input/output timer input/outputs (tio2) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. tio3 gpiog3 b10 110 input /output input/output timer input/outputs (tio3) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. irqa g2 22 input external interrupt request a and b ? the irqa and irqb inputs are asynchronous external interrupt requests that indicate that an external device is requesting service. a schmitt trigger input is used for noise immunity. they can be programmed to be level-sensitive or negative-edge-triggered. if level-sensitive triggering is selected, an external pull-up resistor is required for wired-or operation. irqb f5 23 table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 15 mode a gpioh0 f4 17 input input/output mode select (mode a) ? during the bootstrap process mode a selects one of the eight bootstrap modes. port h gpio (0) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. mode b gpioh1 f3 18 input input/output mode select (mode b) ? during the bootstrap process mode a selects one of the eight bootstrap modes. port h gpio (1) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. mode c gpioh2 f2 19 input input/output mode select (mode c) ? during the bootstrap process mode a selects one of the eight bootstrap modes. port h gpio (2) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. reset k4 39 input reset (reset ) ? this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the mode a, mode b, and mode c pins. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the jtag/enhanced once module. in this case, assert reset , but do not assert trst . rsto k3 38 output reset output (rsto ) ? this output is asserted on any reset condition (external reset, low voltage, software, or cop). rxd0 gpioe0 l10 73 input input/output serial receive data 0 (rxd0) ? this input receives byte- oriented serial data and transfers it to the sci 0 receive shift register. port e gpio (0) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. txd0 gpioe1 l11 74 output(z) input/output serial transmit data 0 (txd0) ? this signal transmits data from the sci 0 transmit data register. port e gpio (1) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. rxd1 gpioe2 b11 107 input input/output serial receive data 1 (rxd1) ? this input receives byte- oriented serial data and transfers it to the sci 1 receive shift register. port e gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
16 DSP56858 preliminary technical data motorola txd1 gpioe3 c10 108 output(z) input/output serial transmit data 1 (txd1) ? this signal transmits data from the sci 1 transmit data register. port e gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. std0 gpioc0 b6 131 output input /output essi transmit data (std0) ? this output pin transmits serial data from the essi transmitter shift register. port c gpio (0) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. srd0 gpioc1 c6 132 input input /output essi receive data (srd0) ? this input pin receives serial data and transfers the data to the essi receive shift register. port c gpio (1) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sck0 gpioc2 c5 133 input /output input/output essi serial clock (sck0) ? this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port c gpio (2) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc00 gpioc3 d6 134 input /output input/output essi serial control pin 0 (sc00) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used either for transmitter1 output or for serial i/o flag 0. port c gpio (3) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc01 gpioc4 b5 135 input /output input/output essi serial control pin 1 (sc01) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used either for transmitter2 output or for serial i/o flag 1. port c gpio (4) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc02 gpioc5 e6 136 input /output input or output essi serial control pin 2 (sc02) ? this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c gpio (5) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 17 std1 gpiod0 e8 99 output input/output essi transmit data (std1) ? this output pin transmits serial data from the essi transmitter shift register. port d gpio (0) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. srd1 gpiod1 e11 100 input input / output essi receive data (srd1) ? this input pin receives serial data and transfers the data to the essi receive shift register. port d gpio (1) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sck1 gpiod2 e9 101 input /output input/output essi serial clock (sck1) ? this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port d gpio (2) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc10 gpiod3 d10 102 input /output input/output essi serial control pin 0 (sc10) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used either for transmitter1 output or for serial i/o flag 0. port d gpio (3) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc11 gpiod4 d11 103 input /output input/output essi serial control pin 1 (sc11) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used either for transmitter2 output or for serial i/o flag 1. port d gpio (4) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. sc12 gpioc5 c11 104 input /output input/output essi serial control pin 2 (sc12) ? this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d gpio (5) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
18 DSP56858 preliminary technical data motorola miso gpiof0 b2 1 input /output input/output spi master in/slave out (miso) ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high- impedance state if the slave device is not selected. the driver on this pin can be configured as an open-drain driver by the spi ? s wired-or mode (wom) bit when this pin is configured for spi operation. port f gpio (0) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. mosi gpiof1 c3 2 input / output (z) input/output spi master out/slave in (mosi) ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. the driver on this pin can be configured as an open- drain driver by the spi ? s wom bit when this pin is configured for spi operation. port f gpio (1) ? this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. sck gpiof2 c2 3 input/ output input/output spi serial clock (sck) ? this bidirectional pin provides a serial bit rate clock for the spi. this gated clock signal is an input to a slave device and is generated as an output by a master device. slave devices ignore the sck signal unless the ss pin is active low. in both master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. the driver on this pin can be configured as an open-drain driver by the spi ? s wom bit when this pin is configured for spi operation. when using wired-or mode, the user must provide an external pull- up device. port f gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. ss gpiof3 d2 4 input input/output spi slave select (ss ) ? this input pin selects a slave device before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. port f gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. xtal h2 27 input/output crystal oscillator output (xtal) ? this output connects the internal crystal oscillator output to an external crystal. if an external clock source other than a crystal oscillator is used, xtal must be used as the input. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
introduction motorola DSP56858 preliminary technical data 19 extal g3 28 input external crystal oscillator input (extal) ? this input should be connected to an external crystal. if an external clock source other than a crystal oscillator is used, extal must be tied off. see section 4.5.2 clko l3 37 output clock output (clko) ? this pin outputs a buffered clock signal. when enabled, this signal is the system clock divided by four. tck l8 60 input test clock input (tck) ? this input pin provides a gated clock to synchronize the test logic and to shift serial data to the jtag/once port. the pin is connected internally to a pull- down resistor. tdi k7 58 input test data input (tdi) ? this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. tdo g6 57 output (z) test data output (tdo) ? this tri-statable output pin provides a serial output data stream from the jtag/enhanced once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. tms j7 59 input test mode select input (tms) ? this input pin is used to sequence the jtag tap controller ? s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. trst l7 56 input test reset (trst ) ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment, since the enhanced once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the enhanced once/jtag module on the dsp. de h6 55 input /output debug event (de ) ? this is an open-drain, bidirectional, active low signal. as an input, it is a means of entering debug mode of operation from an external command controller. as an output, it is a means of acknowledging that the chip has entered debug mode. this pin is connected internally to a weak pull-up resistor. table 3. DSP56858 signal and package information for the 144-pin lqfp and mapbga signal name bga pin no. lqfp pin no. type description
20 DSP56858 preliminary technical data motorola part 4 specifications 4.1 general characteristics the DSP56858 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term ? 5-volt tolerant ? refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the DSP56858 dc/ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 4. absolute maximum ratings characteristic symbol min max unit supply voltage, core v dd 1 1. v dd must not exceed v ddio v ss ? 0.3 v ss + 2.0 v supply voltage, io supply voltage, analog v ddio 2 v ddio 2 2. v ddio and v dda must not differ by more that 0.5v v ssio ? 0.3 v ssa ? 0.3 v ssio + 4.0 v dda + 4.0 v digital input voltages analog input voltages (xtal, extal) v in v ina v ssio ? 0.3 v ssa ? 0.3 v ssio + 5.5 v dda + 0.3 v current drain per pin excluding v dd , gnd i ? 8 ma junction temperature t j -40 120 c storage temperature range t stg -55 150 c
general characteristics motorola DSP56858 preliminary technical data 21 table 5. recommended operating conditions characteristic symbol min max unit supply voltage for logic power v dd 1.62 1.98 v supply voltage for i/o power v ddio 3.0 3.6 v supply voltage for analog power v dda 3.0 3.6 v ambient operating temperature t a -40 85 c pll clock frequency 1 1. assumes clock source is direct clock to extal or crystal oscillator running 2-4mhz. pll must be enabled, locked, and selected. the actual frequency depends on the source clock frequency and programming of the cgm module. f pll ? 240 mhz operating frequency 2 2. master clock is derived from on of the following four sources: f clk = f xtal when the source clock is the direct clock to extal f clk = f pll when pll is selected f clk = f osc when the source clock is the crystal oscillator and pll is not selected f clk = f extal when the source clock is the direct clock to extal and pll is not selected f op ? 120 mhz frequency of peripheral bus f ipb ? 60 mhz frequency of external clock f clk ? 240 mhz frequency of oscillator f osc 24mhz frequency of clock via xtal f xtal ? 240 mhz frequency of clock via extal f extal 24mhz table 6. thermal characteristics 1 1. see section 6.1 for more detail. characteristic symbol value unit 144-pin lqfp 144 mapbga thermal resistance junction-to-ambient (estimated) ja 42.9 36.1 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd ) + p i/o w maximum allowed p d p dmax (t j - t a ) / ja c
22 DSP56858 preliminary technical data motorola 4.2 dc electrical characteristics table 7. dc electrical characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc v dda ? 0.8 v dda v dda + 0.3 v input low voltage (xtal/extal) v ilc -0.3 ? 0.5 v input high voltage v ih 2.0 ? 5.5 v input low voltage v il -0.3 ? 0.8 v input current low (pullups disabled) i il -1 ? 1 a input current high (pullups disabled) i ih -1 ? 1 a output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a output high voltage v oh v dd ? 0.7 ?? v output low voltage v ol ?? 0.4 v output high current i oh 8 ? 16 ma output low current i ol 8 ? 16 ma input capacitance c in ? 8 ? pf output capacitance c out ? 12 ? pf v dd supply current @ nominal voltage and 25 c run 1 deep stop 2 light stop 3 1. run (operating) i dd measured using external square wave clock source (f osc = 4mhz) into xtal. all inputs 0.2v from rail; no dc loads; outputs unloaded. all ports configured as inputs; measured with all modules enabled. pll set to 240mhz out. running core, performing 50% nop and 50% fir. clock at 120 mhz. i dd 4 ? ? ? 70 100 2.6 ? ? ? ma a ma v ddio supply current @ nominal voltage and 25 c run 5 i ddio ? 40 ? ma v dda supply current @ nominal voltage and 25 c deep stop 2 i dda ? 60 ? a low voltage interrupt 6 v ei ? 2.5 2.85 v low voltage interrupt recovery hysteresis v eih ? 50 ? mv power on reset 7 por ? 1.5 2.0 v
supply voltage sequencing and separation cautions motorola DSP56858 preliminary technical data 23 4.3 supply voltage sequencing and separation cautions figure 3 shows two situations to avoid in sequencing the v dd and v ddio, v dda supplies. notes: 1. v dd rising before v ddio , v dda 2. v ddio , v dda rising much faster than v dd figure 3. supply voltage sequencing and separation cautions v dd should not be allowed to rise early (1). this is usually avoided by running the regulator for the v dd supply (1.8v) from the voltage generated by the 3.3v v ddio supply, see figure 4 . this keeps v dd from rising faster than v ddio . v dd should not rise so late that a large voltage difference is allowed between the two supplies (2). typically this situation is avoided by using external discrete diodes in series between supplies, as shown in figure 4 . the series diodes forward bias when the difference between v ddio and v dd reaches approximately 2.1, causing v dd to rise as v ddio ramps up. when the v dd regulator begins proper operation, the difference between supplies will typically be 0.8v and conduction through the diode chain reduces to essentially leakage current. during supply sequencing, the following general relationship should be adhered to: v ddio > v dd > (v ddio - 2.1v) 2. deep stop mode - operation frequency = 4 mhz, pll set to 4 mhz, crystal oscillator and time of day module operat- ing. 3. light stop mode - operation frequency = 120 mhz, pll set to 240 mhz, crystal oscillator and time of day module operating. 4. i dd includes current for core logic, internal memories, and all internal peripheral logic circuitry. 5. running core and performing external memory access. clock at 120 mhz. 6. when v dd drops below v ei max value, an interrupt is generated. 7. power-on reset occurs whenever the digital supply drops below 1.8v. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.8v no matter how long the ramp up rate is. the internally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self-regulates. 3.3v 1.8v time 0 2 1 supplies stable v dd v ddio, v dda dc power supply voltage
24 DSP56858 preliminary technical data motorola in practice, v dda is typically connected directly to v ddio with some filtering. figure 4. example circuit to control supply sequencing 4.4 ac electrical characteristics timing waveforms in section 4.3 are tested with a v il maximum of 0.8v and a v ih minimum of 2.0v for all pins except xtal, which is tested using the input levels in section 4.2 . in figure 5 the levels of v ih and v il for an input signal are shown. figure 5. input signal measurement references figure 6 shows the definitions of the following signal states: active state, when a bus or signal is driven, and enters a low impedance state tri-stated, when a bus or signal is placed in a high impedance state data valid state, when a signal level has reached v ol or v oh data invalid state, when a signal level is in transition between v ol and v oh figure 6. signal states 3.3v regulator 1.8v regulator supply v dd v ddio, v dda v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
external clock operation motorola DSP56858 preliminary technical data 25 4.5 external clock operation the DSP56858 system clock can be derived from a crystal or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal must be connected between the extal and xtal pins. 4.5.1 crystal oscillator the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 9 . in figure 7 a typical crystal oscillator circuit is shown. follow the crystal supplier ? s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. the crystal and associated components should be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 7. crystal oscillator 4.5.2 high speed external clock source (> 4mhz) the recommended method of connecting an external clock is given in figure 8 . the external clock source is connected to xtal and the extal pin is held at ground, v dda , or v dda /2. the tod_sel bit in cgm must be set to 0. figure 8. connecting a high speed external clock signal using xtal 4.5.3 low speed external clock source (2-4mhz) the recommended method of connecting an external clock is given in figure 9 . the external clock source is connected to xtal and the extal pin is held at v dda /2. the tod_sel bit in cgm must be set to 0. sample external crystal parameters: r z = 10m ? tod_sel bit in cgm must be set to 0 f c = 4mhz crystal frequency = 2 ? 4mhz (optimized for 4mhz) extal xtal r z f c DSP56858 xtal extal external gnd, v dda , clock (up to 240mhz) or v dda /2
26 DSP56858 preliminary technical data motorola figure 9. connecting a low speed external clock signal using xtal figure 10. external clock timing table 8. external clock operation timing requirements 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 8 for details on using the recommended connection of an external clock driver. f osc 0 ? 240 mhz clock pulse width 4 t pw 6.25 ?? ns external clock input rise time 2, 4 2. external clock input rise time is measured from 10% to 90%. t rise ?? tbd ns external clock input fall time 3, 4 3. external clock input fall time is measured from 90% to 10%. 4. parameters listed are guaranteed by design. t fall ?? tbd ns table 9. pll timing operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 4mhz input crystal. f osc 244mhz pll output frequency f clk 40 ? 240 mhz pll stabilization time 2 2. this is the minimum time required after the pll setup is changed to ensure reliable operation. t plls ? 110ms DSP56858 xtal extal external clock (2-4mhz) v dda /2 external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
external memory interface timing motorola DSP56858 preliminary technical data 27 4.6 external memory interface timing table 10. external memory interface timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98 v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz, t op = 8.3, f ipb = 60mhz, t ipb = 16.6 1. timing is both wait state and frequency dependent. in the formulas listed, ws = the number of wait states (min. 1) and t op = system clock period. 2. parameters listed are guaranteed by design. 3. emi operates at f ipb rate. wait states are in terms of f ipb periods. 4. shows separation of r/w enables in system cycles (t op ) in data space using consecutive one-word assembly language instructions. characteristic symbol typical min typical max unit address valid to wr asserted t awr 4.36 ? ns wr width asserted wait states > 1 t wr (t ipb *ws) - .81 ? ns d0 ? d15 out valid to wr asserted t wrd 4.57 ? ns data out hold time from wr deasserted t doh 5.37 ? ns data out set up time to wr deasserted wait states > 1 t dos (t ipb *ws) + 4.76 ? ns rd deasserted to address not valid t rda 12.65 ? ns address valid to rd deasserted wait states > 1 t ardd (t ipb *ws) - 2.28 ? ns input data hold to rd deasserted t drd 0 ? ns rd assertion width wait states > 1 t rd (t ipb *ws) - 1.58 ? ns address valid to input data valid wait states > 1 t ad ? (t ipb *ws) - 21.76 ns address valid to rd asserted t arda -1.70 ? ns rd asserted to input data valid wait states > 1 t rdd ? (t ipb *ws) - 21.06 ns wr deasserted to rd asserted t wrrd 4 t op ? ns rd deasserted to rd asserted t rdrd 4 t op x 2 ? ns wr deasserted to wr asserted t wrwr 4 t op x 2 ? ns rd deasserted to wr asserted t rdwr 4 t op x 3 ? ns
28 DSP56858 preliminary technical data motorola figure 11. external memory interface timing 4.7 reset, stop, wait, mode select, and interrupt timing table 11. reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol typical min typical max unit see figure reset assertion to address, data and control signals high impedance t raz ? 11 ns figure 12 minimum reset assertion duration 3 t ra 30 ? ns figure 12 reset deassertion to first external address output t rda ? 120t ns figure 12 edge-sensitive interrupt request width t irw 1t + 3 ? ns figure 13 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm ? 18t ns figure 14 irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig ? 18t ns figure 14 irqa low to first valid interrupt vector address out recovery from wait state 4 t iri ? 13t ns figure 15 irqa width assertion to recover from stop state 5 fast 6 normal 7, 8 t iw 4t 8et ? ? ns ns figure 16 a0 ? a20, c s (see note) wr d0 ? d15 rd note: during read-modify-write instructions and internal instructions, the address lines do not change state. data in data out t awr t arda t ardd t rda t rd t rdrd t rdwr t wrwr t wr t dos t wrd t wrrd t ad t doh t drd t rdd
reset, stop, wait, mode select, and interrupt timing motorola DSP56858 preliminary technical data 29 figure 12. asynchronous reset timing figure 13. external interrupt timing (negative-edge-sensitive) delay from irqa assertion to fetch of first instruction (exiting stop) fast 5 normal 6,7 t if ? ? 13t 25et ns ns figure 16 rsto pulse width 7 normal operation internal reset mode t rsto 128et 8et ? ? ? ? figure 17 1. in the formulas, t = clock cycle. for f op = 120mhz operation and f ipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. 3. at reset, the pll is disabled and bypassed. the part is then put into run mode and t clk assumes the period of the source clock, t xtal , t extal or t osc . 4. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the wait state. this is not the minimum required so that the irqa interrupt is accepted. 5. this interrupt instruction fetch is visible on the pins only in mode 3. 6. fast stop mode: fast stop recovery applies when fast stop mode recovery is requested (omr bit 6 is set to 1). the pll and the master clock are unaffected by stop mode entry. recovery takes one less cycle and t clk will continue with the same value it had before stop mode was entered. 7. normal stop mode: as a power saving feature, normal stop mode disables and bypasses the pll. stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and t clk will resume at the input clock source rate. 8. et = external clock period; for an external crystal frequency of 4mhz, et=250ns. table 11. reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol typical min typical max unit see figure first fetch a0 ? a20, d0 ? d15 cs , rd , wr reset first fetch t rda t ra t raz irqa irqb t irw
30 DSP56858 preliminary technical data motorola figure 14. external level-sensitive interrupt timing figure 15. interrupt from wait state timing figure 16. recovery from stop state using asynchronous interrupt timing figure 17. reset output timing a0 ? a20, cs , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution purpose i/o pin irqa , irqb b) general purpose i/o t ig t idm general instruction fetch irqa , irqb first interrupt vector a0 ? a20, cs , rd , wr t iri not irqa interrupt vector irqa a0 ? a20, cs , rd , wr first instruction fetch t iw t if reset t rsto
host interface port motorola DSP56858 preliminary technical data 31 4.8 host interface port figure 18. dsp-to-host dma read mode table 12. host interface port timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. the formulas: t = clock cycle. f ipb = 60mhz, t = 16.7ns. characteristic symbol min max unit see figure access time tackdv ? 13 ns figure 18 disable time tackdz 3 ? ns figure 18 time to disassert tackreqh 3.5 9 ns figure 18 figure 21 lead time treqackl 0 ? ns figure 18 figure 21 access time tradv ? 13 ns figure 19 figure 20 disable time tradx 5 ? ns figure 19 figure 20 disable time tradz 3 ? ns figure 19 figure 20 setup time tdacks 3 ? ns figure 21 hold time tackdh 1 ? ns figure 21 setup time tadss 3 ? ns figure 22 figure 23 hold time tdsah 1 ? ns figure 22 figure 23 pulse width twds 5 ? ns figure 22 figure 23 time to re-assert 1. after second write in 16-bit mode 2. after first write in 16-bit mode or after write in 8-bit mode tackreql 4t + 5 5 5t + 9 13 ns ns figure 18 , figure 21 hack hd hreq tackdv tackdz treqackl tackreql tackreqh
32 DSP56858 preliminary technical data motorola figure 19. single strobe read mode figure 20. dual strobe read mode figure 21. host-to-dsp dma write mode tradv tradz tradx ha hcs hds hd hrw tradv tradz tradx ha hcs hwr hd hrd hack hreq hd tdacks tackdh treqackl tackreql tackreqh
host interface port motorola DSP56858 preliminary technical data 33 figure 22. single strobe write mode figure 23. dual strobe write mode ha hcs hds hd hrw tadss tadss tdsah tdsah twds tdsah ha hcs hwr hd hrd twds tadss tadss tdsah
34 DSP56858 preliminary technical data motorola 4.9 serial peripheral interface (spi) timing 1. parameters listed are guaranteed by design. table 13. spi timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure cycle time master slave t c 25 25 ? ? ns ns figures 24 , 25 , 26 , 27 enable lead time master slave t eld ? 12.5 ? ? ns ns figure 27 enable lag time master slave t elg ? 12.5 ? ? ns ns figure 27 clock (sclk) high time master slave t ch 9 12.5 ? ? ns ns figures 24 , 25 , 26 , 27 clock (sclk) low time master slave t cl 12 12.5 ? ? ns ns figure 27 data set-up time required for inputs master slave t ds 10 2 ? ? ns ns figures 24 , 25 , 26 , 27 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 24 , 25 , 26 , 27 access time (time to data active from high-impedance state) slave t a 515 ns ns figure 27 disable time (hold time to high-impedance state) slave t d 29 ns ns figure 27 data valid for outputs master slave (after enable edge) t dv ? ? 2 14 ns ns figures 24 , 25 , 26 , 27 data invalid master slave t di 0 0 ? ? ns ns figures 24 , 25 , 26 , 27 rise time master slave t r ? ? 11.5 10.0 ns ns figures 24 , 25 , 26 , 27 fall time master slave t f ? ? 9.7 9.0 ns ns figures 24 , 25 , 26 , 27
serial peripheral interface (spi) timing motorola DSP56858 preliminary technical data 35 figure 24. spi master timing (cpha = 0) figure 25. spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t c t r t f t ch t cl t f t r t ch t ch t dv t dh t ds t di t di (ref) t f t r t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t r t f t c t ch t cl t ch t cl t f t ds t dh t r t di t dv (ref) t dv t f t r
36 DSP56858 preliminary technical data motorola figure 26. spi slave timing (cpha = 0) figure 27. spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1 lsb in ss (input) slave lsb out t ds t cl t cl t di t di t ch t ch t r t r t elg t dh t eld t c t f t f t d t a t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1lsb in ss (input) slave lsb out t elg t di t ds t dh t eld t c t cl t ch t r t f t f t cl t ch t dv t a t dv t r t d
quad timer timing motorola DSP56858 preliminary technical data 37 4.10 quad timer timing figure 28. timer timing enhanced synchronous serial interface (essi) timing table 14. quad timer timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 2t + 3 ? ns timer input high/low period p inhl 1t + 3 ? ns timer output period p out 2t - 3 ? ns timer output high/low period p outhl 1t - 3 ? ns table 15. essi master mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units sck frequency fs ?? 15 2 mhz sck period 3 t sckw 66.7 ?? ns sck high time t sckh 33.4 4 ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ?? 4 ? ns delay from sck high to sc2 (bl) high - master 5 t tfsbhm -1.0 ? 1.0 ns delay from sck high to sc2 (wl) high - master 5 t tfswhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) high - master 5 t rfsbhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) high - master 5 t rfswhm -1.0 ? 1.0 ns delay from sck high to sc2 (bl) low - master 5 t tfsblm -1.0 ? 1.0 ns timer inputs timer outputs p inhl p inhl p in p outhl p outhl p out
38 DSP56858 preliminary technical data motorola delay from sck high to sc2 (wl) low - master 5 t tfswlm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) low - master 5 t rfsblm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) low - master 5 t rfswlm -1.0 ? 1.0 ns sck high to std enable from high impedance - master t txem -0.1 ? 2ns sck high to std valid - master t txvm -0.1 ? 2ns sck high to std not valid - master t txnvm -0.1 ?? ns sck high to std high impedance - master t txhim -4 ? 0ns srd setup time before sc0 low - master t sm 4 ?? ns srd hold time after sc0 low - master t hm 4 ?? ns synchronous operation (in addition to standard internal clock parameters) srd setup time before sck low - master t tsm 4 ?? ns srd hold time after sck low - master t thm 4 ?? ns 1. master mode is internally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for an 120mhz part. 3. all the timings for the essi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 15. essi master mode 1 switching characteristics(continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units
quad timer timing motorola DSP56858 preliminary technical data 39 figure 29. master mode timing diagram table 16: essi slave mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units sck frequency fs ?? 15 2 mhz sck period 3 t sckw 66.7 ?? ns sck high time t sckh 33.4 4 ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ?? 4 ? ns delay from sck high to sc2 (bl) high - slave 5 t tfsbhs -1 ? 29 ns delay from sck high to sc2 (wl) high - slave 5 t tfswhs -1 ? 29 ns delay from sc0 high to sc1 (bl) high - slave 5 t rfsbhs -1 ? 29 ns t thm t tsm t hm t sm t rfswlm t rfswhm t rfblm t rfsbhm t txhim t txnvm t txvm t txem t tfswlm t tfswhm t tfsblm t tfsbhm t sckl t sckw t sckh first bit last bit sck output sc2 (bl) output sc2 (wl) output std sc0 output sc1 (bl) output sc1 (wl) output srd
40 DSP56858 preliminary technical data motorola delay from sc0 high to sc1 (wl) high - slave 5 t rfswhs -1 ? 29 ns delay from sck high to sc2 (bl) low - slave 5 t tfsbls -29 ? 29 ns delay from sck high to sc2 (wl) low - slave 5 t tfswls -29 ? 29 ns delay from sc0 high to sc1 (bl) low - slave 5 t rfsbls -29 ? 29 ns delay from sc0 high to sc1 (wl) low - slave 5 t rfswls -29 ? 29 ns sck high to std enable from high impedance - slave t txes ?? 15 ns sck high to std valid - slave t txvs 4 ? 15 ns sc2 high to std enable from high impedance (first bit) - slave t ftxes 4 ? 15 ns sc2 high to std valid (first bit) - slave t ftxvs 4 ? 15 ns sck high to std not valid - slave t txnvs 4 ? 15 ns sck high to std high impedance - slave t txhis 4 ? 15 ns srd setup time before sc0 low - slave t ss 4 ?? ns srd hold time after sc0 low - slave t hs 4 ?? ns synchronous operation (in addition to standard external clock parameters) srd setup time before sck low - slave t tss 4 ?? ns srd hold time after sck low - slave t ths 4 ?? ns 1. slave mode is externally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for a 120mhz part. 3. all the timings for the essi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 16: essi slave mode 1 switching characteristics(continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units
serial communication interface (sci) timing motorola DSP56858 preliminary technical data 41 figure 30. slave mode clock timing 4.11 serial communication interface (sci) timing table 17. sci timing 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max )/(32) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns t ths t tss t hs t ss t rfswls t rfswhs t rfbls t rfsbhs t txhis t txnvs t ftxvs t txvs t ftxes t txes t tfswls t tfswhs t tfsbls t tfsbhs t sckl t sckw t sckh first bit last bit sck input sc2 (bl) input sc2 (wl) input std sc0 input sc1 (bl) input sc1 (wl) input srd
42 DSP56858 preliminary technical data motorola figure 31. rxd pulse width figure 32. txd pulse width 4.12 jtag timing table 18. jtag timing 1, 3 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 120mhz operation, t = 8.33ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/4 the processor rate. 3. parameters listed are guaranteed by design. f op dc 30 mhz tck cycle time t cy 33.3 ? ns tck clock pulse width t pw 16.6 ? ns tms, tdi data setup time t ds 3 ? ns tms, tdi data hold time t dh 3 ? ns tck low to tdo data valid t dv ? 12 ns tck low to tdo tri-state t ts ? 10 ns trst assertion time t trst 35 ? ns de assertion time t de 4t ? ns rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw
jtag timing motorola DSP56858 preliminary technical data 43 figure 33. test clock input timing diagram figure 34. test access port timing diagram figure 35. trst timing diagram figure 36. enhanced once ? debug event tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tms t ts t dv t ds t dh trst (input) t trst de t de
44 DSP56858 preliminary technical data motorola 4.13 gpio timing figure 37. gpio timing table 19. gpio timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns 2. parameters listed are guaranteed by design. characteristic symbol min max unit gpio input period p in 2t + 3 ? ns gpio input high/low period p inhl 1t + 3 ? ns gpio output period p out 2t - 3 ? ns gpio output high/low period p outhl 1t - 3 ? ns gpio inputs gpio outputs p inhl p inhl p in p outhl p outhl p out
package and pin-out information dsp56853 motorola DSP56858 preliminary technical data 45 part 5 packaging 5.1 package and pin-out information dsp56853 this section contains package and pin-out information for the 144-pin lqfp configuration of the DSP56858. figure 38. top view, DSP56858 144-pin lqfp package orientation mark pin 1 pin 37 pin 109 motorola DSP56858 v dd v ss v ssio v ssio tio3 tio2 tio1 v ddio tio0 v ddio v ddio v ssio v ssio v ssio v dd v ss hds hcs hreq hack d6 d7 d8 d9 d10 std0 srd0 sck0 sc00 sc01 sc02 d11 d12 d13 d14 d15 miso modb v ddio a7 mosi sck ss v ddio v ddio v ssio a6 v s s i o irqa hd0 moda modc rd wr a0 a1 a2 a3 v dd v ss v ss irqb v dda v ssa v ssa xtal extal a4 a5 hd1 hd2 v dd v dd de v ss hd4 v ss v ssio v ssio v ddio v ddio v dd hd5 a 1 5 a11 hd3 trst v ss a14 a13 a12 v ssio v ddio tck tms tdi tdo a10 a9 a8 v ssio v ssio v ddio hd7 hd6 reset rsto clko pin 73 txd1 ha1 v ss a18 rxd1 v ssio v ddio sc12 sc11 v dd a19 s c 1 0 v dd a17 ha2 ha0 sck1 srd1 std1 d5 d4 d3 d2 d1 hrwb cs3 cs2 cs1 cs0 v ssio d0 v ddio a20 a16 txd0 rxd0
46 DSP56858 preliminary technical data motorola table 20. DSP56858 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1miso 37 clko 73 rxd0 109 v dd 2mosi 38 rsto 74 txd0 110 tio3 3sck 39 reset 75 a16 111 tio2 4ss 40 hd3 76 a17 112 tio1 5v ddio 41 hd4 77 a18 113 v ddio 6v ddio 42 hd5 78 a19 114 tio0 7v ssio 43 hd6 79 a20 115 v ssio 8rd 44 hd7 80 v ddio 116 hds 9wr 45 v ddio 81 d0 117 hcs 10 a0 46 v ssio 82 v ssio 118 hreq 11 a1 47 v ssio 83 cs0 119 hack 12 a2 48 a8 84 cs1 120 d6 13 a3 49 a9 85 cs2 121 d7 14 v dd 50 a10 86 cs3 122 d8 15 v ss 51 a11 87 v dd 123 d9 16 v ss 52 v dd 88 v dd 124 d10 17 moda 53 v ss 89 v ss 125 v dd 18 modb 54 v ss 90 ha0 126 v ss 19 modc 55 de 91 ha1 127 v ss 20 v ddio 56 trst 92 ha2 128 v ssio 21 v ssio 57 tdo 93 hrwb 129 v ddio 22 irqa 58 tdi 94 d1 130 v ssio 23 irqb 59 tms 95 d2 131 std0 24 v dda 60 tck 96 d3 132 srd0 25 v ssa 61 v ddio 97 d4 133 sck0
package and pin-out information dsp56853 motorola DSP56858 preliminary technical data 47 26 v ssa 62 v ssio 98 d5 134 sc00 27 xtal 63 a12 99 std1 135 sc01 28 extal 64 a13 100 srd1 136 sc02 29 a4 65 a14 101 sck1 137 d11 30 a5 66 a15 102 sc10 138 d12 31 a6 67 v ddio 103 sc11 139 v ddio 32 a7 68 v ddio 104 sc12 140 v ssio 33 hd0 69 v ssio 105 v ddio 141 v ssio 34 hd1 70 v ssio 106 v ssio 142 d13 35 hd2 71 v ss 107 rxd1 143 d14 36 v dd 72 v dd 108 txd1 144 d15 table 20. DSP56858 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name
48 DSP56858 preliminary technical data motorola figure 39. 144-pin lqfp mechanical information
package and pin-out information dsp56853 motorola DSP56858 preliminary technical data 49 this section contains package and pin-out information for the 144-pin mapbga configuration of the DSP56858. figure 40. bottom-view, DSP56858 144-pin mapbga package metallized mark for pin 1 identification in this area a b c d e f g h j 1 2 3 4 5 6 7 8 9 v ssio k l m 10 11 12 v ssio v ddio v ssio v ddio v ssio v ss v ss v dd v ssio v ddio v dd v ddio d15 miso d12 sc01 std0 d7 hreq tio0 sc12 rxd1 sck v ddio tio3 v ssio mosi d13 sck0 srd0 hack hds tio1 txd1 ss v ddio v ssio rd wr d11 sc00 d6 hcs tio2 a2 sc11 a3 v dd sc10 v ss v dd a1 a0 sc02 d8 std1 sck1 modc srd1 v ss d5 modb moda irqb d14 d10 d9 d2 d3 d4 extal v dd v ss irqa a6 a8 tdo d1 hrwb ha2 cs3 ha1 rsto hd5 cs2 hd3 cs1 cs0 d0 de hd7 a7 a5 xtal hd0 ha0 a4 v ssio v ddio v ssio v ddio a10 tms a12 a18 hd1 a20 v dda a19 v dd reset hd6 a11 tdi a13 a15 a16 a17 hd2 v ss v ssa clko hd4 a9 trst tck a14 rxd0 txd0 v ss v ssio v ssa v dd v ddio v ssio v ssio v dd v ss v ddio v ssio v ddio v ddio v ss10
50 DSP56858 preliminary technical data motorola table 21. DSP56858 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name e5 a0 f7 d10 d8 hcs a5 v ddio e4 a1 d5 d11 j3 hd0 a3 v ddio e3 a2 b4 d12 k2 hd1 c1 v ddio e2 a3 c4 d13 l2 hd2 m10 v ddio j2 a4 f6 d14 j4 hd3 d3 rd h3 a5 b3 d15 l4 hd4 k4 reset g4 a6 h6 de j5 hd5 k3 rsto h4 a7 g3 extal k5 hd6 l10 rxd0 g5 a8 m1 v ssa h5 hd7 b11 rxd1 l5 a9 l1 v ssa c8 hds d6 sc00 j6 a10 g1 v ss b8 hreq b5 sc01 k6 a11 l6 v ss g8 hrwb e6 sc02 j8 a12 d12 v ss g2 irqa d10 sc10 k8 a13 a7 v ss f5 irqb d11 sc11 l9 a14 f1 v ss b2 miso c11 sc12 k9 a15 m7 v ss f4 moda c5 sck0 k10 a16 k12 v ss f3 modb e9 sck1 k11 a17 a8 v ss f2 modc c2 sck j9 a18 d1 v ssio c3 mosi c6 srd0 j10 a19 j1 v ssio k1 v dda e11 srd1 j11 a20 m5 v ssio e1 v dd d2 ss l3 clko m9 v ssio m6 v dd b6 std0 h8 cs0 l12 v ssio f12 v dd e8 std1 h9 cs1 g12 v ssio a9 v dd l8 tck h11 cs2 b12 v ssio m2 v dd k7 tdi h10 cs3 a10 v ssio j12 v dd g6 tdo
package and pin-out information dsp56853 motorola DSP56858 preliminary technical data 51 h7 d0 a4 v ssio e12 v dd b9 tio0 g7 d1 a1 v ssio a12 v dd c9 tio1 f9 d2 a2 v ssio b1 v ddio d9 tio2 f10 d3 m4 v ssio h1 v ddio b10 tio3 f11 d4 m12 v ssio m3 v ddio j7 tms e10 d5 a6 v ssio m8 v ddio l7 trst d7 d6 g10 ha0 m11 v ddio l11 txd0 b7 d7 g11 ha1 h12 v ddio c10 txd1 e7 d8 g9 ha2 c12 v ddio d4 wr f8 d9 c7 hack a11 v ddio h2 xtal table 21. DSP56858 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name
52 DSP56858 preliminary technical data motorola figure 41. 144-pin mapbga mechanical information notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. case 1242a-03 x 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.12 z 0.20 z z rotated 90 clockwise detail k 5 view m-m e 11x x 0.25 y z 0.10 z 3 b 144x 4 dim min max millimeters a --- 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 13.00 bsc e 13.00 bsc e 1.00 bsc y detail k metalized mark for pin 1 identification in this area a b c d e f g h j 1 2 3 4 5 8 9 e 11x 10 11 12 k l m s s s 0.50 bsc
thermal design considerations motorola DSP56858 preliminary technical data 53 part 6 design considerations 6.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: t j = t a + (p d x r ja ) where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: r ja = r jc + r ca where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading
54 DSP56858 preliminary technical data motorola on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 electrical design considerations use the following list of considerations to assure correct dsp operation: provide a low-impedance path from the board power supply to each v dd pin on the dsp, and from the board ground to each v ss (gnd) pin. the minimum bypass requirement is to place six 0.01 ? 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and gnd. bypass the v dd and gnd layers of the pcb with approximately 100 f, preferably with a high- grade capacitor such as a tantalum capacitor. because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and gnd circuits. all inputs must be terminated (i.e., not allowed to float) using cmos levels. take special care to minimize noise levels on the v dda and v ssa pins. when using wired-or mode on the spi or the irqx pins, the user must provide an external pull- up device. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
electrical design considerations motorola DSP56858 preliminary technical data 55 designs that utilize the trst pin for jtag port or enhance once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. the internal por (power on reset) will reset the part at power on with reset asserted or pulled high but requires that trst be asserted at power on.
DSP56858/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1 ? 303 ? 675 ? 2140 or 1 ? 800 ? 441 ? 2447 japan: motorola japan ltd.; sps, technical information center, 3 ? 20 ? 1, minami ? azabu. minato ? ku, tokyo 106 ? 8573 japan. 81 ? 3 ? 3440 ? 3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kon g. 852 ? 26668334 technical information center: 1 ? 800 ? 521 ? 6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all oper ating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for sur gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer s hall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. part 7 ordering information table 22 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 22. DSP56858 ordering information part supply voltage package type pin count frequency (mhz) order number DSP56858 1.8v, 3.3v low-profile quad flat pack (lqfp) 144 120 DSP56858fv120 DSP56858 1.8v, 3.3v map ball grid array (mapbga) 144 120 DSP56858vf120

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